library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity MUL_1_8_7 is port(
	DINA  : in std_logic_vector (15 downto 0);	
	DINB  : in std_logic_vector (15 downto 0);	
	DOUT : out std_logic_vector (15 downto 0));
end MUL_1_8_7;

architecture RTL of MUL_1_8_7 is

	signal MUL_OUT : std_logic_vector(15 downto 0);
	signal S	   : std_logic;
	
	component MULTIPLY_8x8_unsigned is port(
		DINA : in  std_logic_vector(7 downto 0);
		DINB : in  std_logic_vector(7 downto 0);
		DOUT : out std_logic_vector(15 downto 0));
	end component;
	
begin
	process (MUL_OUT,DINA,DINB)
		variable i : natural;
	begin
		if    (MUL_OUT(15) = '1') then
			i := 8;
		elsif	(MUL_OUT(14) = '1') then
			i := 7;
		elsif (MUL_OUT(13) = '1') then
			i := 6;
		elsif (MUL_OUT(12) = '1') then
			i := 5;
		elsif (MUL_OUT(11) = '1') then
			i := 4;
		elsif (MUL_OUT(10) = '1') then
			i := 3;
		elsif (MUL_OUT(9)  = '1') then
			i := 2;
		elsif (MUL_OUT(8)  = '1') then
			i := 1;
		else i := 0;
		end if;
		DOUT <= S & MUL_OUT(i+7 downto i) & ((DINA(6 downto 0) + DINB(6 downto 0))+Conv_Std_Logic_Vector(i, 7));
	end process;
	
	S <= DINA(15) xor DINB(15);
	
MUL_instal:	MULTIPLY_8x8_unsigned port map (
		DINA => DINA(14 downto 7),
		DINB => DINB(14 downto 7),
		DOUT => MUL_OUT);		

end RTL;